Virtualizing Heterogeneous Many-core Platforms
نویسندگان
چکیده
Introduction. The relentless progress of Moore’s Law has periodically inspired major innovations – both in hardware and software – at specific points in time to keep performance growth on pace with transistor density. Industry has reached another such point as it encounters intellectual and engineering challenges in the form of power dissipation, processor-memory performance gap, limits to instruction level parallelism, slower frequency growth, and rising non-recurring engineering costs. As a consequence, when we consider how the large number of transistors that will be supplied at future technology nodes will be used to sustain performance growth, there are some inevitable trends, including i) replication of cores, ii) the use of high volume custom accelerators due to the fact that these devices have small footprint and dramatically less power consumption, and iii) innovations in memory hierarchies. The preceding collectively inspire the development of heterogeneous many-core platforms (HVM) – large scale, heterogeneous systems comprised of homogeneous general purpose cores intermingled with customized heterogeneous cores – accelerators, and using diverse memory and cache hierarchies. Such will be the case both on chip as well as in rack scale and multirack scale systems.
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